A national initiative supported by the Singapore Economic Development Board (EDB) and A*STAR, the 3-Dimensional Through-Silicon Via (3D TSV) Consortium was forged by IME in response to the industry's pressing need to circumvent the scaling limit for semiconductor process technology by stacking integrated circuits (ICs) vertically.

The research collaboratively undertaken by members of the 3D TSV Consortium is carried out in two 18-month phases. Phase one, which is led by IME, serves to establish TSV design and processes for 200mm and 300mm TSV wafer 3D IC assembly, as well as imbue personnel from companies in the semiconductor supply chain with knowledge of 3D TSV design techniques, wafer level processes for TSV, and assembly processes for 3D stacking. Phase two will demonstrate the integration of fully functional mobile devices with TSV on a 300mm wafer process line.

Participating companies in phase one of the first 3D TSV Consortium that commenced in September 2009 include GLOBALFOUNDRIES Singapore Pte. Ltd., STATS ChipPAC Ltd. and United Test and Assembly Center Ltd. The 3D TSV Consortium also enjoys the support of key material providers such as 3MT, Asahi Glass Co., Ltd., Brewer Science Inc., HD Microsystems, Hitachi Chemical Co., Ltd., Nagase & Co., Ltd., Namics Corporation, Nitto Denko (Singapore) Pte. Ltd., OM Group Ultra Pure Chemicals, Sekisui Chemical Co., Ltd., Shanghai Sinyang Semiconductor Materials Co., Ltd., Sumitomo Bakelite Co., Ltd., The Dow Chemical Company and Thin Materials AG. The 3D TSV Consortium is thus able to accelerate the development of materials required for TSV processes, thin wafer handling and packaging assembly processes.

To enquire about the 3D TSV Consortium, please contact Mr. Tan Teck Chun at teckchun@ime.a-star.edu.sg.

Copper wire (Cu-wire) bonding has emerged as an important alternative to gold wire bonding in the semiconductor supply chain due to Cu's lower cost and better material properties. But performance, integrity and reliability issues have continued to hinder its widespread adoption within the industry.

The Cu-Wire Bonding Consortium was established by IME to address these specific challenges. Its primary research pursuit involves the design and fabrication of novel microsensor chips capable of characterising fine pitch Cu-wire bond processes and package reliability under various stress conditions, paving the way for the achievement of reliable Cu-wire bonds. The consortium will also study corrosion and bond degradation related to Cu-wire bonding in harsh environments.

The first Cu-Wire Bonding Consortium was launched in November 2010 and drew key players from the semiconductor industry, including ASM Technology Singapore, Freescale Semiconductor, GLOBALFOUNDRIES, Infineon Technologies Asia Pacific, UNISEM and Atotech S.E.A.

To enquire on the Cu-Wire Bonding Consortium, please contact Mr. Tan Teck Chun at teckchun@ime.a-star.edu.sg.

The Electronic Packaging Research Consortium (EPRC) is a resource and cost sharing platform for electronics packaging research and development in pre-competitive areas of common industry technology needs. Its goal is to inject leading upstream core capability (mainly design and process guidelines) into consortium members so they can apply these enabling technologies to their products and processes. The consortium consists of members from electronics companies, the IC packaging supply chain such as wafer fabs, packaging and testing houses, as well as equipment and material suppliers.

Since its initiation in 1996, the consortium has injected invaluable R&D capabilities into the operation of many multinational and local enterprises in the electronics packaging industry. The consortium has successfully achieved new technological breakthroughs in novel chip size packages for wireless applications, laminate packages for high pin count high performance ICs, and optical packages for communication devices.

EPRC 11

The 11^th Electronic Packaging Research Consortium (EPRC 11) is slated to launch in February 2011, and IME is currently seeking the participation of companies hailing from the Semiconductor, IC Packaging and Electronics industries. » more information

Press Release: IME Launches 11th Electronic Packaging Research Consortium
Industry Forum: 11th Electronic Packaging Research Consortium (EPRC 11) - Proposals Presentation

EPRC 10

The 10th Electronic Packaging Research Consortium (EPRC 10) was successfully launched on 30th June 2009. The two projects under the 18-month programme are 3D-SiP Over Molded Stacked Chips and C2W Bonding, and Embedded Modules. Participating companies include Asahi Glass Co Ltd, Chartered Semiconductor Manufacturing Ltd, EVG Group, Ibiden Singapore Pte Ltd, Kinergy Ltd, NXP Semiconductors Singapore Pte Ltd, Shanghai Sinyang Semiconductor Materials Co Ltd, Tango Systems Inc., and other key industry players. » Press Release: IME Launches 10th Electronic Packaging Research Consortium to Address 3-Dimensional Integrated Circuits

The IME-led Micro-Electro-Mechanical-Systems (MEMS) Consortium brings companies from the MEMS supply chain together on a common technology platform, enabling them to:

1. standardise the MEMS design, process and packaging for multiple applications, such as Post-CMOS (Complementary metal oxide semiconductor) Surface Micromachining MEMS, Bulk micro-machined Silicon on Insulator (SOI) MEMS, and hermetic sealing and wafer level packaging of MEMS devices;
2. develop technical expertise and know-how to facilitate MEMS development, prototyping and manufacturing in Singapore;
3. work collaboratively toward an integrated solution for MEMS manufacturing; and
4. increase their staff's knowledge of MEMS-related technology.

Formed in April 2010 with the support of A*STAR and the Singapore Economic Development Board (EDB), the first MEMS Consortium currently counts Coventor, Inc., EPCOS Pte Ltd (A Group Company of TDK-EPC Corporation), GLOBALFOUNDRIES, Intellisense Software Corp., NEC SCHOTT Components Corporation, Seiko Instruments Inc., and Tango Systems, Inc. among its members.

Together with IME and the Institute of Materials and Research and Engineering (IMRE), the Consortium boasts a wide spectrum of deep capabilities in research and development, wafer fabrication, integrated device manufacturing (IDM), assembly and test, design and computer-aided design (CAD), and equipment and materials.

For enquiries on the MEMS Consortium, please contact Dr. Janak Singh at janak@ime.a-star.edu.sg.