3D Package Using Silicon Interposer Technology for High Wiring Density Interconnection

Microelectronics packaging is driven by the continuous demand for smaller, faster and higher density interconnections at a cheaper cost. Portable product design requires integration of heterogeneous semiconductor technologies in a module for minimum system board area as traditional substrate and packaging technologies may not support the high density and heterogeneous integration required for such applications. Newer packaging approaches, such as Through Silicon Via (TSV) and silicon interposer, are gaining much attention from designers for the realization of high performance Multi-Chip Module (MCM) and System in Package (SiP).

Researchers at IME demonstrated a 3D package using silicon interposer technology for high wiring density interconnection as shown in Figure 1. The result of this development is presented in ECTC 2009 and also reported by Dr. Phil Garrou, "Experience or Prejudice? The Case for Silicon Interposers" on Semiconductor.net.

Fig. 1: 3D Package Using Silicon Interposer

Flip chip packaging with the conventional organic buildup substrate is facing a bottleneck in fine pitch wiring as interconnect density continues to shrink and cost of fabricating finer pitch organic substrate increases significantly. The silicon interposer developed at IME provides high wiring density interconnection, capable of meeting line width < 10um and thousands of I/O pads per square centimeter, with minimized CTE mismatch between the Cu/low-k die. The Cu low-k device packaging with silicon interposer reduces stress in the low-k stack (> 50% reduction) and micro solder bumps creep strain energy density (>20% reduction). The silicon interposer shortens the interconnection from the chip to the substrate. The silicon interposer has thousands of TSV per square centimeter for high density routing. High aspect ratio TSV has been developed for thicker interposer. The silicon interposer heat spreading resistance is much smaller compared organic substrate and the 3D package using silicon interposer technology has been demonstrated for 20W power dissipation.

Home | Top