Innovations in flash memory, such as novel cell architecture and new materials, are required to enter into sub-45nm technology nodes to address the concerns on lithography, coupling ratio, cross-talk between cells, short channel effects (SCE), and state detection with just a few stored electrons faced by the conventional planar flash memory. As a viable solution, 3-D cell architectures receive considerable attention recently, which also allow for ultra-high integration densities.

IME researchers in collaboration with NTU developed, for the first time, an alternative approach to fabricate 3-D vertical flash memory. They demonstrated SONOS memory cells using the vertical gate-all-around (GAA) Si nanowire technology platform. The devices exhibit well-behaved memory characteristics in terms of the program/erase window, retention and endurance properties.

Shown in Fig. 1 are the TEM image along with the transient characteristics of the vertical Si nanowire SONOS device for both programming and erasing processes (P/E), respectively. The F/N tunneling, a positive pulse at Gate with S/D grounded (V_G > 0, V_S=V_D=0), was used to program the SONOS cell. A drain potential of +5V was applied to facilitate the erasing process (V_G < 0, V_S=0, V_D=+5V) which was otherwise found slow perhaps due to the presence of n-type channel as a result of some n-type doping of the channel from S/D and gate implant and activations processes. The n-type channel formation is supported by the negative threshold voltage (VTH), usually reported in normally ON depletion mode devices. The P/E characteristics shows a memory window of ~2.5V when P/E is done for 1ms at ±18V. Usually, in SONOS NVM, the erasing speed is slower than programming due to higher effective mass of holes, but as demonstrated, the additional drain voltage applied during erasing process has balanced the two. Significant improvement in the memory window is expected with optimization of ONO layer and by inclusion of nano-crystals to engineer the trap layer. The fabricated vertical SiNW SONOS memory showed good high temperature (85°C) retention and endurance characteristics.

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Fig. 1: (a) TEM Image (b) Programming (left) and erase (right) characteristics of a vertical GAA SiNW SONOS memory with wire diameter ~ 50 nm and L_g=150nm. F/N tunneling is used for programming while a drain bias of 5V was applied for erasing process. The V_TH was extracted from Id-Vg characteristics using constant drain current (Id) equal to 10-7A/µm, where circumference of the wire was taken into account for the normalization purpose.

As compared to the lateral SiNW flash memory, it is noted that additional SONOS flash memories can be further built on top of the existing one along the vertical SiNW, which paves the way to realize 3-D ultra-high density flash technology. 3-D flash technology will have much compact memory with better speed, low operating voltage and low power consumption thus will be very suitable for all handheld mobile and implantable devices/systems. Our future objectives are to optimize the gate stack for optimum P/E window and speed and to attempt for 3D stacking of cells for vertical NAND array demonstration.